1. Field of the Invention
The present invention relates to high density memory devices, and particularly to memory devices in which multiple planes of memory cells are arranged to provide a three-dimensional 3D array.
2. Description of Related Art
The subject matter discussed in this section should not be assumed to be prior art merely as a result of its mention in this section. Similarly, a problem mentioned in this section or associated with the subject matter provided as background should not be assumed to have been previously recognized in the prior art. The subject matter in this section merely represents different approaches, which in and of themselves can also correspond to implementations of the claimed technology.
As critical dimensions of devices in integrated circuits shrink to the limits of common memory cell technologies, designers have been looking to techniques for stacking multiple planes of memory cells to achieve greater storage capacity, and to achieve lower costs per bit. For example, thin-film transistor techniques are applied to charge trapping memory technologies in Lai, et al., “A Multi-Layer Stackable Thin-Film Transistor (TFT) NAND-Type Flash Memory,” IEEE Int'l Electron Devices Meeting, 11-13 Dec. 2006; and in Jung et al., “Three Dimensionally Stacked NAND Flash Memory Technology Using Stacking Single Crystal Si Layers on ILD and TANOS Structure for Beyond 30 nm Node,” IEEE Int'l Electron Devices Meeting, 11-13 Dec. 2006.
Another structure that provides vertical NAND cells in a charge trapping memory technology is described in Katsumata, et al., “Pipe-shaped BiCS Flash Memory with 16 Stacked Layers and Multi-Level-Cell Operation for Ultra High Density Storage Devices,” 2009 Symposium on VLSI Technology Digest of Technical Papers, 2009. The structure described in Katsumata et al. includes a vertical NAND gate, using silicon-oxide-nitride-oxide-silicon SONOS charge trapping technology to create a storage site at each gate/vertical channel interface. The memory structure is based on a column of semiconductor material arranged as the vertical channel for the NAND gate, with a lower select gate adjacent the substrate, and an upper select gate on top. A plurality of horizontal word lines is formed using planar word line layers that intersect with the columns, forming a so-called gate all around the cell at each layer.
Another example of a memory structure includes a vertical thin-channel memory which can be configured as a 3D NAND flash memory. Vertical thin-channel cells in the memory are arranged along vertical active pillars which comprise U-shaped semiconductor thin-films, providing a structure with semiconductor thin-films on two sides electrically separated along the length of the pillar and electrically connected at the bottom. The active pillars are disposed between stacks of conductive strips operable as word lines with memory elements in between. As a result of this structure, two memory cells are formed per frustum of the active pillar, where each memory cell at the frustum includes a channel in the semiconductor thin-film on one side of the active pillar. A gap in insulation material between opposing vertical channel films may be included to suppress interference between back-to-back channels in U-turn architecture.
Methods of manufacturing memory structures including such active pillars with vertical thin-channels and a gap in the insulation material between opposing vertical channel films may include forming a thin-film semiconductor layer over a plurality of stacks of conductive strips. This is followed by filling trenches between the thin-film semiconductor layer with an insulation material. The insulation material includes a gap which will become gaps between opposing vertical channel films. The partially formed device is then patterned and etched to form thin vertical channel films on opposing sides of the trenches. However, because the insulation material includes a gap, the deep hole etching process through the insulating material may not be uniform. This non-uniformness may cause irregular profiles and deformities of the deep holes and therefore non-uniformness in the resulting structures of the device. These irregularities and deformities are not desirable because they may result negatively on device performance.
It is therefore desirable to provide a method of manufacturing memory structures including active pillars with vertical thin-channels and a gap in the insulation material between opposing vertical channel films where the vertical channel films are formed without irregularities.